1. Field of the Invention
This invention relates to manufacture of multichip integrated circuit device configurations.
2. Description of the Related Art
In the manufacture of integrated circuit devices, system level integration on a single highly wirable substrate is desirable for achieving higher system functionality and performance. Namely, it is desirable to integrate high performance logic, dense memory, RF circuitry, other analog functions, microelectro-mechanical function, and so forth, on a single substrate. However, the technologies used in these individual functions are diverse, and they employ highly varied base technologies, different costs and yields. While it is possible to integrate a few of these components in a given semiconductor technology, such an approach requires compromises in technology with a concomitant degrading of some of the technology attributes, e.g., a reduction of DRAM density in a logic based merged logic and technology, or a reduction of logic performance in a DRAM based merged logic and DRAM technology.
Advances occurring in semiconductor processing have permitted the scale of individual integrated circuit devices to be shrunk to make it possible to incorporate increasing amounts of functionality in a single integrated circuit chip. For example, sixteen 1 MBIT Dynamic Random Access Memory (DRAM) chips of equal size in 1984 required a total chip area of 800 mm.sup.2, while a single 16 MBIT design containing the same functionality in 1990 required only 110 mm.sup.2. Thus, although the individual chip size has increased by approximately 50%, the net chip area has been reduced by a factor of 8. Accordingly, as integrated circuit chips are required to incorporate more and more functionality, the size of the chips has been steadily increasing.
However, there are practical problems associated with continually increasing the maximum chip size. A first set of problems relates to the physical limits of present day fabrication equipment. For example, state-of-the-art manufacturing lithography equipment commonly used to expose high resolution patterns through masks onto semiconductor substrates effectively limits chip size to the size of the lithography exposure field of the equipment. The size of the direct exposure field of state-of-the-art manufacturing lithography equipment in the mid 1990s is generally on the order of 25 mm in diameter, allowing square chip design exposure of about 324 mm.sup.2 (18 mm.times.18 mm). Most DRAM chip designs in development are rectangular and tend to be 20 mm.times.10 mm, or larger. A solution to the exposure field/stitching problem is to develop fabrication equipment having a larger exposure field and, therefore, the capability to manufacture larger chips without stitching masks together. However, such a solution would require massive financial investment in research and development.
Another problem relates to the general trend of wafer yields decreasing with increasing chip size. That is, it has been observed that as chip area increases, the effective chip yields reduce nearly linearly. The decrease in yield with increasing chip size can be attributed to the fact that for the same quality of semiconductor, any defect existing in a larger chip results in an overall greater area waste than is the case with smaller chip wafers. As chip size increases, the cost of manufacturing due to yield degradation becomes prohibitive.
Conventional multi-chip modules (MCM's) have avoided the problems associated with producing large chips by combining a plurality of small-sized chips in a larger package. For example, U.S. Pat. No. 4,489,364, assigned to IBM, discloses a ceramic chip carrier for supporting an array of chips by means of solder balls, such as controlled collapsed chip connections (i.e., C4). However, such MCMs tend to be extremely expensive due to their multilayered ceramic features and they require significantly more area than the net overall area of the combined set of chips. As a consequence, the wiring density is not sufficiently high for current requirements in many cases.
Prior to the present invention, there was an unsatisfied need for a multichip integration scheme for combining, in close proximity, a plurality of semiconductor integrated circuit chips.